1. Field of the Invention
The present invention relates to a semiconductor device, particularly, to a semiconductor device having a packaged semiconductor chip and a method of manufacturing the same.
2. Description of the Related Art
In recent years, a high operating speed and the miniaturization of the semiconductor element mounted inside a semiconductor device are being promoted with progress in the operating speed of the semiconductor device and in the function performed by the semi-conductor device. Also, the miniaturization of the semiconductor element is promoted by the formation of a fine multi-wiring in the semiconductor element.
However, the miniaturization causes an increase in the parasitic capacitance between the adjacent wirings included in the semiconductor element so as to lower the operating speed of the semiconductor element. Such being the situation, the interlayer insulating film formed between the adjacent wirings is formed of a low dielectric constant film (low-k film) in order to suppress the parasitic capacitance between the adjacent wirings. As a result, the parasitic capacitance between the adjacent wirings is lowered so as to suppress the lowering in the operating speed of the semiconductor element.
Also, in order to further decrease the dielectric constant of the low-k film, the low-k film is made porous in place of a film having a high density such as a SiO2 film. It is possible to further decrease the parasitic capacitance between the adjacent wirings by using such a porous low-k film as an interlayer insulating film, with the result that it is possible to prevent the operating speed of the semiconductor element from being lowered.
On the other hand, a BGA (Ball Grid Array) of, for example, a flip-chip type is being propagated as a semiconductor package capable of coping with the high operating speed and the miniaturization required in recent years. In the flip-chip type BGA, a semi-conductor element is mounted to a package substrate having a multi-layered wiring of a high density such that the surface of the semiconductor element equipped with electrode pads of the semiconductor element is allowed to face the package substrate. In the mounting step, the package substrate is connected to the semiconductor element by the C4 (Controlled Collapse Chip Connection) technology using as a solder bump and, then, the clearance between the package substrate and the semiconductor element is sealed by an under-fill.
As a relating technology of this kind, Japanese Patent Disclosure (Kokai) No. 2001-244362 discloses a flip-chip type BGA having a low thermal resistance.
However, in the case of using a porous low-k film as an interlayer insulating film included in the semiconductor element, the mechanical strength of the low-k film is lowered. Therefore, since the semiconductor element is mounted to the package substrate such that the surface of the semiconductor element is allowed to face the package substrate in, for example, the flip-chip type BGA referred to above, stress is generated within the semiconductor element because of the difference in the thermal expansion coefficient between the package substrate and the semiconductor element. As a result, a serious problem is generated that the low-k film having the lowered mechanical strength is broken.